In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited onto or removed from a substrate surface. Thin layers of conducting, semiconducting, and dielectric materials may be deposited onto the substrate surface by a number of deposition techniques. Deposition techniques common in modern microelectronics processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and electrochemical plating (ECP).
As layers of materials are sequentially deposited onto and removed from the substrate, the uppermost surface of the substrate may become non-planar and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Compositions and methods for planarizing or polishing the surface of a substrate are well known in the art. Chemical-mechanical planarization, or chemical-mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes a chemical composition, known as a CMP composition or more simply as a polishing composition (also referred to as a polishing slurry) for selective removal of material from the substrate. Polishing compositions typically are applied to a substrate by contacting the surface of the substrate with a polishing pad (e.g., polishing cloth or polishing disk) saturated with the polishing composition. The polishing of the substrate typically is further aided by the chemical activity of the polishing composition and/or the mechanical activity of an abrasive suspended in the polishing composition or incorporated into the polishing pad (e.g., fixed abrasive polishing pad).
Silicon dioxide-based dielectric layers are frequently used to isolate metal-containing circuit lines formed on a substrate. Because the dielectric constant of silicon dioxide-based dielectric materials is relatively high, i.e., approximately 3.9 or higher (depending on factors such as residual moisture content), the capacitance between the conductive layers is also relatively high, which limits the speed (frequency) at which a circuit can operate. Interlevel dielectric (ILD) materials having lower dielectric constants relative to silicon dioxide can be used to provide electrical isolation and increase the frequency at which the circuit can operate. Polymer films have been considered for use as such ILD materials because they have relatively low dielectric constants and low intrinsic stress levels. Polymer films are also important in through-silica via (TSV) applications.
Methods of polishing polymer films employ the mechanical properties of abrasive particles to polish the polymer. Thus, removal rates are directly related to the hardness of the abrasive particle, the solid content level in the polishing composition, and the specific polishing conditions employed. To achieve a higher removal rate of the polymer film, hard abrasive particles, relatively high solid contents, and aggressive polishing conditions have been required. However, abrasive particles can cause several defects during polishing, including scratches on the surface of the polymer, which limit performance.
Thus, it would be highly desirable to have a chemical-mechanical polishing composition that employs the chemical properties of the composition to a more significant extent to polish polymer films, thereby avoiding the need for a high solids content while increasing the removal rate of the polymer film and exhibiting good defect performance. A need remains for a polishing composition and polishing methods that will exhibit desirable planarization efficiency, uniformity, and removal rate during the polishing and planarization of substrates containing polymer films, while minimizing defectivity, such as surface imperfections and damage to underlying structures and topography during polishing and planarization. The invention provides such a polishing composition and methods. These and other advantages of the invention, as well as additional inventive features, will be apparent from the description of the invention provided herein.